Wikidata:Property proposal/Cache

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   Under discussion
Descriptionhardware component that stores data for computing
Representscache (Q165596)
Data typeItem
Allowed valuesone or multiple items that hold integer numbers
Allowed unitsByte or exponential values (kilobyte, megabyte, etc.)
Example 1AMD Phenom II X6 1090T (Q66481199)L1 cache (Q28972913): 8 x 64 KB (4-way set associative) + 8 x 32 KB (8-way set associative), L2 cache (Q12635161): 8 x 512 KB (16-way set associative exclusive caches), L3 cache (Q28972917): 6 MB (48-way set associative cachevalue, shared)[1]
Example 2AMD Ryzen Threadripper 1900X (Q56062710)L1 cache (Q28972913): 6 x 64 KB (2-way set associative instruction caches) + 6 x 64 KB (2-way set associative data caches), L2 cache (Q12635161): 6 x 512 KB (16-way set associative exclusive caches), L3 cache (Q28972917): 2 x 8 MB (16-way set associative)[2]
Example 3Pentium N3700 → L1 cache (Q28972913): 4 x 32 KB (8-way set associative) + 4 x 24 KB (6-way set associative), L2 cache (Q12635161): 2 x 1 MB (16-way set associative)[3]
Sourceen:Cache (computing)
Planned useCan be used for every object that has some form of cache


I'm working on AMD Phenom II X6 1090T (Q66481199) and want to include as much information has possible so that I can use it as template. The cache information is a very important part of a CPU.

There were already two property proposals that suggested the same, but ended in the middle of nowhere and were withdrawn afterall.

The structure would be like this (example below keep the parts that should be read together):

  • Cache: (property)
    • L1/2/3/4 cache (item)
      • L1/2/3/4 cache value
        • value information (applies to)

Information could also not only be added about the type and it's size, but also

  • cache latency
  • cache connection (how many lanes the caches uses to connect to the CPU/IO unit)
  • cache storage type (is the cache only responsible to hold a specific type of data like instructions or data)
  • cache exclusiveness (is the cache per CPU core, per CPU module (eg. AMD Bulldozer architecture) or is it shared for all)
  • cache area (how much area does the cache use. This could be interesting with AMDs chiplet design when maybe different types of cache sits on different chiplets in different manufacturing sizes)

Since there already were some comments on the last proposals I will try to answer them:

  • @GPSLeo:: Should we use multiple properties?: I don't care if there is one or more properties. I want to make it as flexible as possible so that the cache of rather exotic CPUs are much easiert to include when they are only items.
  • @Visite fortuitement prolongée:: We could use volatile random-access memory capacity (P2928) with qualifiers: Is all cache in every IT product volatile? The property seems more to be used in items where there is a fixed ammount of maximum RAM (eg. phones). This usecase is also the only listed case for as property example.
  • @TomT0m:: We could use has part (P527): It would be the same layout, but I do not want to jam all the cache into something that could also house all other values in the item. Some items use has parts of the class (P2670) (Q56062710#P2670) and uses (P2283) (Q51963118#P2283). Since there seems to be no clear wy of how to include such an information there are already multiple forms of it.

Example for AMD Phenom II X6 1090T (Q66481199):

  • L1 cache:
    • 6 x 64 KB
      • applies to associative instruction cache
      • connection 2-way
      • dispersion one per core
    • 6 x 64 KB
      • applies to associative data cache
      • connection 2-way
      • dispersion one per core
  • L2 cache:
    • 6 x 512 KB
      • applies to associative exclusive cache
      • connection 16-way
      • dispersion one per core
  • L3 cache:
    • 6 MB
      • applies to associative cache
      • connection 48-way
      • dispersion shared


Ping to all missing: @ديفيد عادل وهبة خليل 2:, @Dhx1:, @GNUtoo:, @Amitie 10g:, @MisterSanderson:, @Tobias1984:, @Srittau:, @Jsamwrites:, @Tinker Bell:, @SixTwoEight:
Ruud Koot
Daniel Mietchen
Tinker Bell
Jasc PL
Tris T7
Peb Aryan
FWVH (passionné d'informatique et d'électronique)
Pictogram voting comment.svg Notified participants of WikiProject Informatics

If you have any idea or comment don't hesitate to post it! --D-Kuru (talk) 15:28, 2 December 2019 (UTC)

  • Symbol oppose vote.svg Oppose I already proposed this, and found a workaround, without needing a property for Cache. --Amitie 10g (talk) 18:05, 2 December 2019 (UTC)
If you already found a workaround please show me the example above in a real item --D-Kuru (talk) 18:48, 2 December 2019 (UTC)
  • Symbol oppose vote.svg Oppose I don't see any problem using has part (P527): has parts of the class (P2670) is intended to use with subclasses, not instances, so it doesn't apply here (although I think it can be confusing sometimes). And uses (P2283) is intended to use with objects that are not part of the subject, that's no the case here. --Tinker Bell 18:42, 2 December 2019 (UTC)